DG-ACC-JADP-1【PDF 79/116 页】JTAG ADAPTER FOR CC 9C W-9C

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MODULE SPECIFICATIONS

Module / SO-DIMM signal characteristics

Pin

SIgnal name

Internal

OD

I/O

Description

I/O

Notes / Bootstrapping (BS)

U/D

(mA)

class

21

22

ADDRESS_2

MFGI_GPIO[72]

12

8

O

I/O

Address bus signal

4

1

CSO parallel port, see Note 4

Reserved - 15K pull-up on the

module

23

24

ADDRESS_3

GPIO[71]

12

8

O

I/O

Address bus signal

4

1

CSO parallel port, see Note 4

15K pull-up on the module

(12C_SDA)

25

26

ADDRESS_4

GPIO[70]

12

8

O

I/O

Address bus signal

4

1

CSO parallel port, see Note 4

15K pull-up on the module

(12_SCL)

27

28

ADDRESS_5

GPIO[69]

12

8

O

I/O

Address bus signal

4

1

CSO parallel port, see Note 4

Add 10-15K pull-up if not used.

29

30

GND

GND

31

GPIO[27]

U

4

I/O

2

32

No connect

33

GPIO[26]

U

4

I/O

2

34

MFGO_GPIO[67]

8

I/O

1

Reserved - Green module LED

35

GPIO[25]

U

4

I/O

2

36

GPIO[66]

8

I/O

1

Reserved - yellow LED + Reset/FF

37

GPIO[24]

U

4

I/O

3

BS: Chip select 1 MSB data width

bootstrap select (Default=0, 16-bit

width)

38

GPIO[23]

U

4

I/O

2

39

40

GND

GND

41

42

43

44

45

GPIO[47]

GPIO[22]

GPIO[46]

GPIO[21]

GPIO[45]

U

U

U

U

U

2

4

2

4

2

I/O

I/O

I/O

I/O

I/O

2

2

2

2

2

46

GPIO[20]

U

8

I/O

3

BS: Chip select 0 data width

bootstrap select (Default=0, 16-bit

width)

47

GPIO[44]

U

2

I/O

3

BS: Endian mode (Default=0, Big if

NOR; 1, Little NAND)

48

GPIO[43]

2

I/O

1

Add 10-15K pull-up if not used

www.digiembedded.com

71

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